If both clocks are connected together, the shift register always is one clock pulse ahead of the storage register. Both the shift register clock (SRCLK) and storage register clock (RCLK) are positive-edge triggered. When the output-enable (OE) input is high, the outputs are in the high-impedance state. The shift register has a direct overriding clear (SRCLR) input, serial (SER) input, and serial outputs for cascading. Separate clocks are provided for both the shift and storage register. The storage register has parallel 3-state outputs. The SN74HC595 contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. 8-Bit Serial-In, Parallel-Out Shift Wide Operating Voltage Range 6 V High-Current 3-State Outputs Can Drive To 15 LSTTL Loads Low Power Consumption: 80-mA (Max) ICC tpd 13 ns (Typ) ☖-mA Output Drive 5 V Low Input Current: 1 mA (Max) Shift Register Has Direct ClearĬontrolled Baseline One Assembly/Test Site One Fabrication Site Available in Military (55☌/125☌) Temperature Range (1) Extended Product Life Cycle Extended Product-Change Notification Product TraceabilityĪdditional temperature ranges available - contact factory
0 Comments
Leave a Reply. |